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MC33298 Octal Serial Switch with Serial Peripheral Interface I/O
The MC33298 is an eight output low side power switch with 8 bit serial input control. The MC33298 is a versatile circuit designed for automotive applications, but is well suited for other environments. The MC33298 incorporates SMARTMOSTM technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power MOSFETs. The MC33298 interfaces directly with a microcontroller to control various inductive or incandescent loads. The circuit's innovative monitoring and protection features are: very low standby current, cascadable fault reporting, internal 65 V clamp on each output, output specific diagnostics, and independent shutdown of outputs. The MC33298 is parametrically specified over a temperature range of - 40C TA +125C ambient temperature and 9.0 V VPWR 16 V supply. The economical 20 pin DIP and SO-24 wide body surface mount plastic packages make the MC33298 very cost effective. * Designed to Operate Over Wide Supply Voltages of 5.5 V to 26.5 V
OCTAL SERIAL SWITCH (SPI Input/Output)
SEMICONDUCTOR TECHNICAL DATA
20 1
* * * * * * * * * * * * * * *
Interfaces Directly to Microprocessor Using SPI Protocol SPI Communication for Control and Fault Reporting 8-Bit Serial I/O is CMOS Compatible 3.0 A Peak Current Outputs with Maximum RDS(on) of 0.45 at 25C Outputs are Current Limited to 3.0 A to 6.0 A for Driving Incandescent Lamp Loads Output Voltages Clamped to 65 V During Inductive Switching Maximum Sleep Current (IPWR) of 50 A with VDD 2.0 V Maximum of 4.0 mA IDD During Operation Maximum of 2.0 mA IPWR During Operation with All Outputs "On" Open Load Detection (Outputs "Off") Overvoltage Detection and Shutdown Each Output has Independent Over Temperature Detection and Shutdown Output Mode Programmable for Sustained Current Limit or Shutdown Short Circuit Detect and Shutdown with Automatic Retry for Every Write Cycle Serial Operation Guaranteed to 2.0 MHz
DIP 1 2 3 4 5 6 - - 7 8 9 10 11 12 13 14 15 16 - - 17 18 19 20
P SUFFIX PLASTIC PACKAGE CASE 738 DIP (16+2+2)
24 1
DW SUFFIX PLASTIC PACKAGE CASE 751E SOP (16+4+4)L
PIN CONNECTIONS
Function Output 7 Output 6 SCLK SI Ground Ground Ground Ground SO CSB Output 5 Output 4 Output 3 Output 2 SFPD VDD Ground Ground Ground Ground VPWR Reset Output 1 Output 0 SOP-24L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Simplified Application
SFPD VDD VPWR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Gnd +Vbat
SFPD CSB Micro- controller with Bus SCLK SI Reset SO CMOS Input Logic CMOS Serial Shift Registers and Latches
Updrain DMOS Output Switches and Sense Circuits
ORDERING INFORMATION
Device MC33298P MC33298DW Tested Operating Temperature Range TC = - 40 to +125C Package DIP SOP-24L
Rev 2
This device contains 1,200 active transistors.
(c) Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
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MC33298
Figure 1. Simplified Block Diagram
VPWR Output 0 Bias 65 V
VDD SFPD
Overvoltage Detect 20 A OVD RB SFPDB SFL CSB SCLK SI SO CSI CSBI
Voltage Regulator GE OT SF OF SPI Interface Logic
Gate Control
Reset
To Gates 1-7
20 A Fault Timers
Outputs 1-7
CSB
Open Load Detect
ILimit RS
SCLK Short Circuit Detect
SI
Grounds SO Serial D/O Line Driver Over Temperature Detect From Detectors 1 to 7
FAULT OPERATION
SERIAL OUTPUT (SO) PIN REPORTS Overvoltage Over Temperature Over Current Output "On," Open Load Fault Output "Off," Open Load Fault DEVICE SHUTDOWNS Overvoltage Total device shutdown at VPWR = 28-36 V. Re-operates when overvoltage is removed with all outputs assuming an off state upon recovery from overvoltage. All device registers are automatically reset (cleared) during shutdown. Only the output experiencing an over temperature shuts down. Only the output experiencing an over current condition shuts down at 3.0 A to 6.0 A after a 25 s to 100 s delay, with SFPD pin grounded. All outputs will continue to operate in a current limit mode, with no shutdown, if the SPFD pin is at 5.0 V. Overvoltage condition reported. Fault reported by Serial Output (SO) pin. SO pin reports short to battery/supply or over current condition. Not reported. SO pin reports output "off" open load condition.
Over Temperature Over Current
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MOTOROLA ANALOG IC DEVICE DATA
MC33298
MAXIMUM RATINGS (All voltages are with respect to ground, unless otherwise noted.)
Rating Power Supply Voltage Steady-State Transient Conditions (Note1) Logic Supply Voltage (Note 2) Input Pin Voltage (Note 3) Output Clamp Voltage (Note 4) (2.0 mA Iout 0.5 A) Output Self-Limit Current Continuous Per Output Current (Note 5) ESD Voltage Human Body Model (Note 6) Machine Model (Note 7) Output Clamp Energy (Note 8) Repetitive: TJ = 25C TJ = 125C Non-Repetitive: TJ = 25C TJ = 125C Recommended Frequency of SPI Operation (Note 9) Storage Temperature Operating Case Temperature Operating Junction Temperature Power Dissipation (TA = 25C) (Note 10) Soldering Temperature (for 10 seconds) Thermal Resistance, Junction-to-Ambient (Note 11) Plastic Package, Case 738: All Outputs "On" (Note 12) Single Output "On" (Note 13) SOP-24 Package, Case 751E: All Outputs "On" (Note 12) Single Output (Note 13) IOUT(lim) IOUT(cont) VESD1 VESD2 Eclamp 100 30 2.0 0.5 fSPI Tstg TC TJ PD Tsolder RJA 31 37 34 40 2.0 - 55 to +150 - 40 to +125 - 40 to +150 3.0 260 mJ mJ J J MHz C C C W C C/W Symbol VPWR(sus) VPWR(pk) VDD VIN VOUT(off) 50 to 75 3.0 to 6.0 1.0 2000 200 A A V V Value -1.5 to 26.5 -13 to 60 - 0.3 to 7.0 - 0.3 to 7.0 Unit V V V V V
NOTES: 1. Transient capability with external 100 resistor connected in series with VPWR pin and supply. 2. Exceeding these limits may cause a malfunction or permanent damage to the device. 3. Exceeding voltage limits on SCLK, SI, CSB, SFPD, or Reset pins may cause permanent damage to the device. 4. With output "off." 5. Continuous output rating so long as maximum junction temperature is not exceeded. (See Figure 21 and 22 for more details). 6. ESD1 testing is performed in accordance with the Human Body Model (CZap = 100 pF, RZap = 1500 ). 7. ESD2 testing is performed in accordance with the Machine Model (CZap = 100 pF, RZap = 0 ). 8. Maximum output clamp energy capability at indicated Junction Temperature using single pulse method. See Figure 19 for more details. 9. Guaranteed and production tested for 2.0 MHz SPI operation but has been demonstrated to operate to 8.5 MHz @ 25C. 10. Maximum power dissipation at indicated junction temperature with no heat sink used. See Figures 20, 21, and 22 for more details. 11. See Figure 20 for Thermal Model. 12. Thermal resistance from Junction-to-Ambient with all outputs "on" and dissipating equal power. 13. Thermal resistance from Junction-to-Ambient with a single output "on."
MOTOROLA ANALOG IC DEVICE DATA
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MC33298
STATIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V,
- 40C TC 125C, unless otherwise noted.) Characteristic POWER INPUT Supply Voltage Range Quasi-Functional (Note 1) Full Operational Supply Current (all Outputs "On," Iout = 0.5 A) (Note 2) Sleep State Supply Current (VDD = 0.5 V) Sleep State Output Leakage Current (per Output, VDD = 0.5 V) Overvoltage Shutdown Overvoltage Shutdown Hysteresis Logic Supply Voltage Logic Supply Current (with any combination of Outputs "On") Logic Supply Undervoltage Lockout Threshold (Note 3) POWER OUTPUT Drain-to-Source "On" Resistance (Iout = 0.5 A, TJ = 25C) VPWR = 5.5 V VPWR = 9.0 V VPWR = 13 V Drain-to-Source "On" Resistance (Iout = 0.5 A, TJ = 150C) VPWR = 5.5 V VPWR = 9.0 V VPWR = 13 V Output Self-Limiting Current Outputs Programmed "On", Vout = 0.6 VDD Output Fault Detect Threshold (Note 4) Output Programmed "Off" Output "Off" Open Load Detect Current (Note 5) Output Programmed "Off," Vout = 0.6 VDD Output Clamp Voltage 2.0 mA Iout 200 mA Output Leakage Current (VDD 2.0 V) (Note 6) Over Temperature Shutdown (Outputs "Off") (Note 7) Over Temperature Shutdown Hysteresis (Note 7) RDS(on) - - - RDS(on) - - - IOUT(lim) 3.0 VOUTth(F) 0.6 IOCO 30 VOK 50 IOUT(lkg) TLIM TLIM(hys) - 50 155 - 60 0 170 10 75 50 185 20 A C C 50 100 V 0.7 0.8 A 4.0 6.0 VDD - 0.75 0.65 1.8 0.9 0.8 A - 0.4 0.35 1.0 0.5 0.45 V VPWR(qf) VPWR(fo) IPWR(on) IPWR(ss) IOUT(ss) VOV VOV(hys) VDD IDD VDD(uvlo) 5.5 9.0 - - - 28 0.2 4.5 - 2.0 - - 1.0 1.0 - - - - - - 9.0 26.5 2.0 50 50 36 1.5 5.5 4.0 4.5 mA A A V V V mA V Symbol Min Typ Max Unit
NOTES: 1. SPI inputs and outputs operational; Fault reporting may not be fully operational within this voltage range. 2. Value reflects normal operation (no faults) with all outputs "on." Each "on" output contributes approximately 20 A to IPWR. Each output experiencing a "soft short" condition contributes approximately 0.5 mA to IPWR. A "soft short" is defined as any load current causing the output source current to self-limit. A "hard" output short is a very low impedance short to supply. 3. For VDD less than the Undervoltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled. 4. Output fault detect threshold with outputs programmed "off." Output fault detect thresholds are the same for output opens and shorts. 5. Output "Off" Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open condition when the specific output is commanded to be "off." 6. Output leakage current measured with output "off" and at 16 V. 7. This parameter is guaranteed by design but is not production tested.
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MOTOROLA ANALOG IC DEVICE DATA
MC33298
STATIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V,
- 40C TC 125C, unless otherwise noted.) Characteristic DIGITAL INTERFACE Input Logic High Voltage (Note 1) Input Logic Low Voltage (Note 2) Input Logic Voltage Hysteresis (Note 3) Input Logic Current (Note 4) Reset Pull-Up Current (Reset = 0.7 VDD) SFPD Pull-Down Current (SFPD = 0.2 VDD) SO High State Output Voltage (IOH = 1.0 mA) SO Low State Output Voltage (IOL = -1.6 mA) SO Tri-State Leakage Current (CSB = 0.7 VDD, 0 V VSO VDD) Input Capacitance (0 V VDD 5.5 V) (Note 5) SO Tri-State Capacitance (0 V VDD 5.5 V) (Note 6) VIH VIL VI(hys) IIN IRSTB ISFPD VSOH VSOL ISOT CIN CSOT 0.7 0.0 50 -10 10 10 VDD -1.0 V - - 10 - - - - 100 0 22 22 VDD - 0.6 V 0.2 0 - - 1.0 0.2 500 10 50 50 - 0.4 10 12 20 VDD VDD mV A A A V V A pF pF Symbol Min Typ Max Unit
NOTES: 1. Upper logic threshold voltage range applies to SI, CSB, SCLK, Reset, and SFPD input signals. 2. Lower logic threshold voltage range applies to SI, CSB, SCLK, Reset, and SFPD input signals. 3. Only the SFPD and Reset inputs have hysteresis. This parameter is guaranteed by design but is not production tested. 4. Input current of SCLK, SI, and CSB logic control inputs. 5. Input capacitance of SI, CSB, SCLK, Reset, and SFPD for 0 V VDD 5.5 V. This parameter is guaranteed by design, but is not production tested. 6. Tri-state capacitance of SO for 0 V VDD 5.5 V. This parameter is guaranteed by design but is not production tested.
Figure 2. Input Timing Switch Characteristics
VIH
RSTB
0.2 VDD twRSTB VIH VIL
CSB
0.2 VDD tlead 0.7 VDD twSCLKH tr tlag VIH 0.2 VDD tSISU 0.7 VDD twSCLKL tSI(hold) Valid 0.2 VDD Don't Care tf VIH Valid Don't Care VIL VIL VIL
SCLK
SI
Don't Care
MOTOROLA ANALOG IC DEVICE DATA
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MC33298
DYNAMIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V VDD 5.5 V,
9.0 V VPWR 16 V, - 40C TC 125C, unless otherwise noted.) Characteristic POWER OUTPUT TIMING Output Rise Time (VPWR = 13 V, RL = 26 ) (Note 1) Output Fall Time (VPWR = 13 V, RL = 26 ) (Note 1) Output Turn "On" Delay Time (VPWR = 13 V, RL = 26 ) (Note 2) Output Turn "Off" Delay Time (VPWR = 13 V, RL = 26 ) (Note 3) Output Short Fault Disable Report Delay (Note 4) SFPD = 0.2 x VDD Output "Off" Fault Report Delay (Note 5) SFPD = 0.2 x VDD tr tf tdly(on) tdly(off) tdly(sf) 25 tdly(off) 25 50 100 50 100 s 0.4 0.4 1.0 1.0 1.5 2.5 5.0 5.0 20 20 15 15 s s s s s Symbol Min Typ Max Unit
NOTES: 1. Output Rise and Fall time respectively measured across a 26 resistive load at 10% to 90% and 90% to 10% voltage points. 2. Output Turn "On" Delay time measured from rising edge of CSB to 50% of output "off" Vout voltage with RL = 26 resistive load (see Figure 7 and 9). 3. Output Turn "Off" Delay time measured from rising edge of CSB to 50% of output "off" Vout voltage with RL = 26 resistive load (see Figure 7 and 9). 4. Output Short Fault Disable Report Delay measured from rising edge of CSB to Iout = 2.0 A point with output "on," Vout = 5.0 V, and SFPD = 0.2 x VDD (see Figure 8 and 10). 5. Output "Off" Fault Report Delay measured from 50% points of rising edge of CSB to rising edge of output (see Figure 9).
DYNAMIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V VDD 5.5 V,
9.0 V VPWR 16 V, - 40C TC 125C, unless otherwise noted.) Characteristic DIGITAL INTERFACE TIMING SCLK Clock Period (Note 6) SCLK Clock High Time SCLK Clock Low Time Required Low State Duration for Reset (VIL 0.2 VDD) (Note 1) Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to SI (Required Hold Time) SO Rise Time (CL = 200 pF) SO Fall Time (CL = 200 pF) SI, CSB, SCLK Incoming Signal Rise Time (Note 2) SI, CSB, SCLK Incoming Signal Fall TIme (Note 2) Time from Falling Edge of CSB to SO Low Impedance (Note 3) HIgh Impedance (Note 4) Time from Rising Edge of SCLK to SO Data Valid (Note 5) 0.2 VDD SO 0.8 VDD, CL = 200 pF tpSCLK twSCLKH twSCLKL twRSTB tlead tlag tSISU tSI(hold) trSO tfSO trSI tfSI tSO(en) tSO(dis) tvalid - 50 125 ns 500 175 175 250 250 250 125 125 - - - - - - - - - 50 50 50 25 25 25 25 - - - - - - - - - - - - 75 75 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min Typ Max Unit
NOTES: 1. Reset Low duration measured with outputs enabled and going to "off" or disabled condition. 2. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 3. Time required for output status data to be available for use at SO. 4. Time required for output status data to be terminated at SO. 5. Time required to obtain valid data out from SO following the rise of SCLK. 6. Clock period includes 75 ns rise plus 75 ns fall transition time in addition to clock high and low time.
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MOTOROLA ANALOG IC DEVICE DATA
MC33298
Figure 3. Valid Data Delay Time and Valid Time Test Circuit
VDD = 5.0 V
Figure 4. Enable and Disable Time Test Circuit
VDD = 5.0 V
VPull-Up = 2.5 V
MC33298
SCLK Under Test SO CL = 200 pF CSB
MC33298
Under Test
RL = 2.0 k SO CL = 20 pF
CL represents the total capacitance of the test fixture and probe.
CL represents the total capacitance of the test fixture and probe.
Figure 5. Vaild Data Delay Time and Valid Time Waveforms
trSI 0.7 VDD (2.5 V) SCLK 10 ns 50% tfSI 10 ns 5.0 V 0.2 VDD 0 SO CSB
Figure 6. Enable and Disable Time Waveforms
trSI 0.7 VDD 0.2 VDD (2.5 V) tSO(en) 50% VOL VOH 50% tSO(en) tSO(dis) VOL VOH SO (Low-to-High) tfSI 90% 50% 10% tSO(dis) VOH
10 ns
10 ns 5.0 V
0
tdly(lh) SO (Low-to-High) SO (High-to-Low) 0.7 VDD tdly(hl) 0.2 VDD tvalid trSO tfSO
0.7 VDD
VOH
(High-to-Low)
0.2 VDD
VOL
VOL
SO (low-to-high) is for an output with internal conditions such that the low-to-high transition of CSB causes the SO output to switch from high-to-low.
NOTES: 1. SO (high-to-low) waveform is for SO output with internal conditions such that SO output is low except when an output is disabled as a result of detecting a circuit fault with CSB in a High Logic state (e.g., open load). 2. SO (low-to-high) waveform is for SO output with internal conditions such that SO output is high except when an output is disabled as a result of detecting a circuit fault with CSB in a High Logic state (e.g., shorted load).
MOTOROLA ANALOG IC DEVICE DATA
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MC33298
Figure 7. Switching Time Test Circuit
VDD = 5.0 V
Figure 8. Output Fault Unlatch Disable Delay Test Circuit
VDD = 5.0 V VPWR = 11 V IL = 2.0 A (Output "On") Output CL = 20 pF
VPWR = 14 V
MC33298
CSB Under Test
RL = 26 Output CL
MC33298
CSB Under Test
CL represents the total capacitance of the test fixture and probe.
CL represents the total capacitance of the test fixture and probe.
Figure 9. Turn-On/Off Waveforms
Figure 10. Output Fault Unlatch Disable Delay Waveforms
trSI 5.0 V tfSI 90% 10%
trSI
10 ns
tfSI 90% 50%
10 ns
10 ns 50% 90%
10 ns 5.0 V 0
CSB
10%
90% 50%
10% 0 CSB 10%
tdly(off) Output Voltage Waveform 1 50%
14 V Output Voltage Waveform tdly(off) Output Current Waveform 50% 0 Voff = 11 V 50% Von = 5.0 V
VOL 14 V 50% tdly(on) VOL
Output Voltage Waveform 2
IO(CL)
NOTES: 1. tdly(on) and tdly(off) are turn-on and turn-off propagation delay times. 2. Waveform 1 is an output programmed from an "on" to an "off" state. 3. Waveform 2 is an output programmed from an "off" to an "on" state.
NOTES: 1. tpdly(off) is the output fault unlatch disable propagation delay time required to correctly report an output fault after CSB rises. Represents an output commanded "on" while having an existing output short (overcurrent) to supply. 2. SFPD pin 0.2 V.
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MOTOROLA ANALOG IC DEVICE DATA
MC33298
CIRCUIT DESCRIPTION
Introduction The MC33298 was conceived, specified, designed, and developed for automotive applications. It is an eight output low side power switch having 8-bit serial control. The MC33298 incorporates SMARTMOSTM technology having effective 2.0 CMOS logic, bipolar/MOS analog circuitry, and independent state of the art double diffused MOS (DMOS) power output transistors. Many benefits are realized as a direct result of using this mixed technology. A simplified block diagram of the MC33298 is shown in Figure 1. Where bipolar devices require considerable control current for their operation, structured MOS devices, since they are voltage controlled, require only transient gate charging current affording a significant decrease in power consumption. The CMOS capability of the SMARTMOSTM process allows significant amounts of logic to be economically incorporated into the monolithic design. In addition, bipolar/MOS analog circuits embedded within the updrain power DMOS output transistors monitor and provide fast, independent protection control functions for each individual output. All outputs have internal 65 V at 0.5 A independent output voltage clamps to provide fast inductive turn-off and transient protection. The MC33298 uses high efficiency updrain power DMOS output transistors exhibiting very low drain to source "on" resistance values (RDS(on) 0.45 ) and dense CMOS control logic. Operational bias currents of less than 4.0 mA (1.0 mA typical) with any combination of outputs "on" are the result of using this mixed technology and would not be possible with bipolar structures. To accomplish a comparable functional feature set using a bipolar structure approach would result in a device requiring hundreds of milliamperes of internal bias and control current. This would represent a very large amount of power to be consumed by the device itself and not available for load use. In operation the MC33298 functions as an eight output serial switch serving as a microcontroller (MCU) bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. The MC33298 directly interfaces to an MCU and operates at system clock serial frequencies in excess of 2.0 MHz using a Synchronous Peripheral Interface (SPI) for control and diagnostic readout. Figure 11 shows the basic SPI configuration between an MCU and one MC33298. Figure 11. SPI Interface with Microcontroller
MC68HCXX Microcontroller MOSI Shift Register MISO SCLK Receive Buffer Parallel Ports Reset To Logic SO SI Shift Register
MC33298
CSB
The circuit can also be used in a variety of other applications in the computer, telecommunications, and industrial fields. It is parametrically specified over an input "battery"/supply range of 9.0 V to 16 V but is designed to operate over a considerably wider range of 5.5 V to 26.5 V. The design incorporates the use of Logic Level MOSFETs as output devices. These MOSFETs are sufficiently turned "on" with a gate voltage of less than 5.0 V thus eliminating the need for an internal charge pump. Each output is identically sized and independent in operation. The efficiency of each output transistor is such that with as little as 9.0 V supply (VPWR), the maximum RDS(on) of an output at room temperature is 0.45 (0.35 typical) and increases to only 1.0 (0.5 typical) as VPWR is decreased to 5.5 V. All inputs are compatible with 5.0 V CMOS logic levels and incorporate negative or inverted logic. Whenever an input is programmed to a logic low state (< 1.0 V) the corresponding low side switched output being controlled will be active low and turned "on." Conversely, whenever an input is programmed to a logic high state (> 3.0 V), the output being controlled will be high and turned "off."
Figure 12. MC33298 SPI System Daisy Chain
SCLK Parallel Port CSB MISO SO IRQ MC33298 SI SO MC33298 SI SO MC33298 SI SO MC33298 SI SCLK CSB SCLK CSB SCLK CSB SCLK
MC68XX Microcontroller SPI
MOSI
8 Outputs
8 Outputs
8 Outputs
8 Outputs
MOTOROLA ANALOG IC DEVICE DATA
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MC33298
One main advantage of the MC33298 is the serial port which when coupled to an MCU, receives "on"/"off" commands from the MCU and in return transmits the drain status of the device's output switches. Many devices can be "daisy-chained" together to form a larger system (see Figure 12). Note in this example that only one dedicated MCU parallel port (aside from the required SPI) is needed for chip select to control 32 possible loads. Multiple MC33298 devices can also be controlled in a parallel input fashion using SPI (see Figure 13). This figure shows a possible 24 loads being controlled by only three dedicated parallel MCU ports used for chip select. Figure 13. Parallel Input SPI Control
MC33298 SI SCLK CSB MC33298 SI SCLK A0 Parallel A1 Ports A2 CSB MC33298 SI SCLK CSB 8 Outputs MC68XX Microcontroller SPI (Master) B0 A0 B1 Parallel A1 Ports A2 8-Bit VDD SS MC68XX Microcontroller SPI (Alternate Master) B0 A0 B1 Parallel A1 Ports A2 8-Bit VDD SS SCLK MISO MOSI SCLK MISO MOSI MC33298 CSB SCLK SO SI 8-Bit 8 Outputs MC33298 CSB SCLK 8-Bit SO SI 8 Outputs 8 Outputs
SPI System Attributes The SPI system is flexible enough to communicate directly with numerous standard peripherals and MCUs available from Motorola and other semiconductor manufacturers. SPI reduces the number of pins necessary for input/output (I/O) on the MC33298. It also offers an easy means of expanding the I/O function using few MCU pins. The SPI system of communication consists of the MCU transmitting, and in return, receiving one databit of information per clock cycle. Databits of information are simultaneously transmitted by one pin, Microcontroller Out Serial In (MOSI), and received by another pin, Microcontroller In Serial Out (MISO), of the MCU. Some features of SPI are: * Full Duplex, Three-Wire Synchronous Data Transfer * Each Microcontroller can be a Master or a Slave * Provides Write Collision Flag Protection * Provides End of Message Interrupt Flag * Four I/Os associated with SPI (MOSI, MISO, SCLK, SS) The only drawbacks to SPI are that an MCU is required for efficient operational control and, in contrast to parallel input control, is slower at performing pulse width modulating (PWM) functions. Figure 14. Multiple MCU SPI Control
MOSI SCLK MC68XX Microconttoller SPI
Figure 14 shows a basic method of controlling multiple MC33298 devices using two MCUs. A system can have only one master MCU at any given instant of time and one or more slave MCUs. The master MCU supplies the system clock signal (top MCU designated the master); the lower MCU being the slave. It is possible to have a system with more than one master but not at the same time. Only when the master is not communicating can a slave communicate. MCU master control is switched through the use of the slave select (SS) pin of the MCUs. A master will become a slave when it detects a logic low state on its SS pin. These basic examples make the MC33298 very attractive for applications where a large number of loads need be controlled efficiently. The popular Synchronous Serial Peripheral Interface (SPI) protocol is incorporated, to this end, to communicate efficiently with the MCU.
8 Outputs
MC33298 CSB SCLK 8-Bit SO SI
8 Outputs
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MOTOROLA ANALOG IC DEVICE DATA
MC33298
PIN FUNCTION DESCRIPTION
CSB Pin T he s y s t em MC U s e l e c ts th e M C 3 3 2 98 to be communicated with through the use of the CSB pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the MC33298 and vise versa. Clocked-in data from the MCU is transferred from the MC33298 shift register and latched into the power outputs on the rising edge of the CSB signal. On the falling edge of the CSB signal, drain status information is transferred from the power outputs and loaded into the device's shift register. The CSB pin also controls the output driver of the serial output pin. Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowing information to be transferred from the MC33298 to the MCU. To avoid any spurious data, it is essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic low state. SCLK Pin The system clock pin (SCLK) clocks the internal shift registers of the MC33298. The serial input pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It is essential that the SCLK pin be in a logic low state whenever chip select bar pin (CSB) makes any transition. For this reason, it is recommended though not necessary, that the SCLK pin be kept in a low logic state as long as the device is not accessed (CSB in logic high state). When CSB is in a logic high state, any signal at the SCLK and SI pin is ignored and SO is tristated (high impedance). See the Data Transfer Timing diagram of Figure 16. SI Pin This pin is for the input of serial instruction data. SI information is read in on the falling edge of SCLK. A logic high state present on this pin when the SCLK signal rises will program a specific output "off," and in turn, turns "off" the specific output on the rising edge of the CSB signal. Conversely, a logic low state present on the SI pin will program the output "on," and in turn, turns "on" the specific output on the rising edge of the CSB signal. To program the eight outputs of the MC33298 "on" or "off," an eight bit serial stream of data is required to be entered into the SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For each rise of the SCLK signal, with CSB held in a logic low state, a databit instruction ("on" or "off") is loaded into the shift register per the databit SI state. The shift register is full after eight bits of information have been entered. To preserve data integrity, care should be taken to not transition SI as SCLK transitions from a low to high logic state. SO Pin The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin goes to a logic low state. The SO data reports the drain status, either high or low. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is "off" and not faulted, the corresponding SO databit is a high state. When an output is "on," and there is no fault, the corresponding databit on the SO pin will be a low logic state. The SI/SO shifting of data follows a first-in-first-out protocol with both MOTOROLA ANALOG IC DEVICE DATA input and output words transferring the Most Significant Bit (MSB) first. The SO pin is not affected by the status of the Reset pin. Reset Pin The MC33298 Reset pin is active low and used to clear the SPI shift register and in doing so sets all output switches "off." With the device in a system with an MCU; upon initial system power up, the MCU holds the Reset pin of the device in a logic low state ensuring all outputs to be "off" until both the VDD and VPWR pin voltages are adequate for predictable operation. After the MC33298 is reset, the MCU is ready to assert system control with all output switches initially "off." If the VPWR pin of the MC33298 experiences a low voltage, following normal operation, the MCU should pull the Reset pin low so as to shutdown the outputs and clear the input data register. The Reset pin is active low and has an internal pull-up incorporated to ensure operational predictability should the external pull-up of the MCU open circuit. The internal pull-up is only 20 A to afford safe and easy interfacing to the MCU. The Reset pin of the MC33298 should be pulled to a logic low state for a duration of at least 250 ns to ensure reliable reset. A simple power "on" reset delay of the system can be programmed through the use of an RC network comprised of a shunt capacitor from the Reset pin to Ground and a resistor to VDD (See Figure 15). Care should be exercised to ensure proper discharge of the capacitor so as to not adversely delay the reset nor damage the MCU should the MCU pull the Reset line low and yet accomplish initialization for turn "on" delay. It may be easier to incorporate delay into the software program and use a parallel port pin of the MCU to control the MC33298 Reset pin. Figure 15. Power "On" Reset
VDD
RDLY Reset MCU CDLY
20 A Reset
MC33298 SFPD Pin The Short Fault Protect Disable (SFPD) pin is used to disable the over current latch-off. This feature allows control of incandescent loads where in-rush currents exceed the device's analog current limits. Essentially the SFPD pin determines whether the MC33298 output(s) will instantly shut down upon sensing an output short or remain "on" in a current limiting mode of operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is tied to VDD = 5.0 V the MC33298 output(s) will remain "on" in a current limited mode of operation upon encountering a load short to supply. If the SFPD pin is grounded, a short circuit will immediately shut down only the output affected. Other outputs not having a fault condition will operate normally. The short circuit operation is addressed in more detail later. 11
12 Figure 16. Data Transfer Timing
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 OD* OD* OD* OD* OD* OD* D0* D1* D2* D3* D4* D5* D6* D7* Old Data New Data DO7 Old Data New Data DO0
CSB
SCLK
SI
D0
D1
SO
OD*
OD*
MC33298
Output 7
Output 0
NOTES: 1. 2. 3. 4. 5.
Reset pin is in a logic high state during the above operation. D0, D1, D2, ..., and D15 relate to the ordered entry of program data into the MC33298 with D0/D8 bits (MSB) corresponding to Output 7 and D7/D15 corresponding to Output 0. D0*, D1*, D2*, ..., and D7* relate to the ordered data out of the MC33298 with D0* bit (MSB) corresponding to Output 7. OD* corresponds to Old Databits. For brevity, only DO7 and DO0 are shown which respectively correspond to Output 7 and Output 0.
Figure 16.
Data Transfer Timing (General) CSB High-to-Low CSB Low-to-High SO SI SO pin is enabled. Output Status information transferred to Output Shift Register. Data from the Shift Register is transferred to the Output Power Switches. Will change state on the rising edge of the SCLK pin signal. Will accept data on the falling edge of the SCLK pin signal.
MOTOROLA ANALOG IC DEVICE DATA
MC33298
Power Consumption The MC33298P has extremely low power consumption in both the operating and standby modes. In the standby or "sleep" mode, with VDD 2.0 V, the current consumed by the VPWR pin is less than 50 A. In the operating mode, the current drawn by the VDD pin is less than 4.0 mA (1.0 mA typical) while the current drawn at the VPWR pin is 2.0 mA maximum (1.0 mA typical). During normal operation, turning outputs "on" increases IPWR by only 20 A per output. Each output experiencing a "soft short" (overcurrent conditions just under the current limit), adds 0.5 mA to the IPWR current. Paralleling of Outputs Using MOSFETs as output switches allows the connection of any combination of outputs together. MOSFETs have an inherent positive temperature coefficient thermal feedback which modulates RDS(on) providing balanced current sharing between outputs without destructive operation (bipolar outputs could not be paralleled in this fashion as thermal run-away would likely occur). The device can even be operated with all outputs tied together. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(on) while the Output Off Open Load Detect Currents and the Output Current Limits increase correspondingly (by a factor of eight if all outputs are paralleled). Less than 56 m RDS(on) with current limiting of 24 to 48 A will result if all outputs are paralleled together. There will be no change in the Overvoltage detect or the "Off" Output Threshold Voltage Range. The advantage of paralleling outputs within the same MC33298 affords the existence of minimal RDS(on) and output clamp voltage variation between outputs. Typically, the variation of RDS(on) between outputs of the same device is less than is 0.5%. The variation in clamp voltages (which could affect dynamic current sharing) is less than 5%. Paralleling outputs from two or more devices is possible but not recommended. This is because there is no guarantee that the RDS(on) and clamp voltage of the two devices will match. System level thermal design analysis and verification should be conducted whenever paralleling outputs.
FAULT LOGIC OPERATION
General The MCU can perform a parity check of the fault logic operation by comparing the command 8-bit word to the status 8-bit word. Assume that after system reset, the MCU first sends an 8-bit command word, Command Word 1, to the MC33298. Each output that is to be turned "on" will have its corresponding databit low. Refer to the Data Transfer Timing diagram of Figure 16. As this word, Command Word 1, is being written into the shift register of the MC33298, a status word is being simultaneously written out and received by the MCU. However, the word being received by the MCU is the status of the previous write word to the MC33298, Status Word 0. If the command word of the MCU is written a second time (Command Word 2 = Command Word 1), the word received by the MCU, Status Word 2, is the status of Command Word 1. The timing diagram shown in Figure 16 depicts this operation. Status Word 2 is then compared with Command Word 1. The MCU will Exclusive OR Status Word 2 with Command Word 1 to determine if the two words are identical. If the two words are identical, no faults exist. The timing between the two write words must be greater than 100 s to receive proper drain status. The system databus integrity may be tested by writing two like words to the MC33298 within a few microseconds of each other. Initial System Setup Timing The MCU can monitor two kinds of faults: (1) Communication errors on the data bus and (2) Actual faults of the output loads. After initial system start up or reset, the MCU will write one word to the MC33298. If the word is repeated within a few microseconds (say 5) of the first word, the word received by the MCU, at the end of the repeated word, serves as a confirmation of data bus integrity (1). At startup, the MC33298 will take 25 to 100 s before a repeat of the first word can give the actual status of the outputs. Therefore, the first word should be repeated at least 100 s later to verify the status of the outputs. The SO of the MC33298 will indicate any one of four faults. The four possible faults are Over Temperature, Output Off Open Fault, Short Fault (overcurrent), and V PWR Overvoltage Fault. All of these faults, with the exception of the Overvoltage Fault, are output specific. Over Temperature Detect, Output Off Open Detect, and Output Short Detect are dedicated to each output separately such that the outputs are independent in operation. A VPWR Overvoltage Detect is of a "global" nature causing all outputs to be turned "off." Over Temperature Fault Patent pending Over Temperature Detect and shutdown circuits are specifically incorporated for each individual output. The shutdown that follows an Over Temperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155C to 185C. When an output shuts down due to an Over Temperature Fault, no other outputs are affected. The MCU recognizes the fault since the output was commanded to be "on" and the status word indicates that it is "off." A maximum hysteresis of 20C ensures an adequate time delay between output turn "off" and recovery. This avoids a very rapid turn "on" and turn "off" of the device around the Over Temperature threshold. When the temperature falls below the recovery level for the Over Temperature Fault, the device will turn "on" only if the Command Word during the next write cycle indicates the output should be turned "on." Overvoltage Fault An Overvoltage condition on the VPWR pin will cause the MC33298 to shut down all outputs until the overvoltage condition is removed and the device is re-programmed by the SPI. The overvoltage threshold on the VPWR pin is specified as 28 V to 36 V with 1.0 V typical hysteresis. Following the overvoltage condition, the next write cycle sends the SO pin the hexadecimal word $FF (all ones) indicating all outputs are turned "off." In this way, potentially dangerous timing problems are avoided and the MCU reset
MOTOROLA ANALOG IC DEVICE DATA
13
MC33298
routine ensures an orderly startup of the loads. The MC33298 does not detect an overvoltage on the VDD pin. Other external circuitry, such as the Motorola MC33161 Universal Voltage Monitor, is necessary to accomplish this function. Output Off Open Load Fault An Output Off Open Load Fault is the detection and reporting of an "open" load when the corresponding output is disabled (input in a logic high state). To understand the operation of the Open Load Fault detect circuit, see Figure 17. The Output Off Open Load Fault is detected by comparing the drain voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. Figure 17. Output "Off" Open Load Detect
VPWR RL MOSFET "Off" Output 50 A
Therefore, the load resistance necessary to prevent false open load fault reporting is (using Ohm's Law) equal to 92 k or less. During output switching, especially with capacitive loads, a false Output Off Open Load Fault may be triggered. To prevent this false fault from being reported an internal fault filter of 25 to 100 s is incorporated. The duration for which a false fault may be reported is a function of the load impedance (RL, CL, LL), RDS(on), and Cout of the MOSFET as well as the supply voltage, VPWR. The rising edge of CSB triggers a built in fault delay timer which must time out (25 to 100 s) before the fault comparator is enabled to detect a faulted threshold. The circuit automatically returns to normal operation once the condition causing the Open Load Fault is removed. Shorted Load Fault A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater than the current limit. There are three safety circuits progressively in operation during load short conditions which afford system protection: 1) The device's output current is monitored in an analog fashion using a SENSEFETTM approach and limited; 2) The device's output current limit threshold is sensed by monitoring the MOSFET drain voltage; and 3) The device's output thermal limit is sensed and when attained causes only the specific faulted output to be latched "off," allowing remaining outputs to operate normally. All three protection mechanisms are incorporated in each output affording robust independent output operation. The analog current limit circuit is always active and monitors the output drain current. An overcurrent condition causes the gate control circuitry to reduce the gate to source voltage imposed on the output MOSFET which re-establishes the load current in compliance with current limit (3.0 to 6.0 A) range. The time required for the current limit circuitry to act is less than 20 s. Therefore, currents higher than 3.0 to 6.0 A will never be seen for more than 20 s (a typical duration is 10 s). If the current of an output attempts to exceed the predetermined limit of 3.0 to 6.0 A (4.0 A nominal), the VDS voltage will exceed the VThres voltage and the overcurrent comparator will be tripped as shown in Figure 18. Figure 18. Short Circuit Detect and Analog Current Limiting Circuit MC33298
High = Fault MOSFET "On" Digital Output VPWR RL
MC33298
Low = Fault
VThres 0.6 to 0.8 x VDD
An Output Off Open Load Fault is indicated when the output voltage is less than the Output Threshold Voltage (VThres) of 0.6 to 0.8 x VDD. Since the MC33298 outputs function as switches, during normal operation, each MOSFET output should either be completely turned "on" or "off." By design the threshold voltage was selected to be between the "on" and "off" voltage of the MOSFET. During normal operation, the "on" state VDS voltage of the MOSFET is less than the threshold voltage and the "off" state VDS voltage is greater than the threshold voltage. This design approach affords using the same threshold comparator for Output Open Load Detect in the "off" state and Short Circuit Detect in the "on" state. See Figure 18 for an understanding of the Short Circuit Detect circuit. With VDD = 5.0 V, an "off" state output voltage of less than 3.0 V will be detected as an Output Off Open Load Fault while voltages greater than 4.0 V will not be detected as a fault. The MC33298 has an internal pull-down current source of 50 A, as shown in Figure 17, between the MOSFET drain and ground. This prevents the output from floating up to VPWR if there is an open load or internal wirebond failure. The internal comparator compares the drain voltage with a reference voltage, VThres (0.6 to 0.8 x VDD). If the output voltage is less than this reference voltage, the MC33298 will declare the condition to be an open load fault. During steady-state operation, the minimum load resistance (RL) needed to prevent false fault reporting during normal operation can be found as follows: VPWR = 9.0 V (min) ILCO = 50 A VThres (max) = (0.8 x 5.5)V = 4.4 V
Analog
Vref
VThres 0.6 to 0.8 x VDD
14
MOTOROLA ANALOG IC DEVICE DATA
MC33298
The status of SFPD will determine whether the MC33298 will shut down or continue to operate in an analog current limited mode until either the short circuit is removed or thermal shutdown is reached. Grounding the SFPD pin will enable the short fault protection shutdown circuitry. Consider a load short (output short to supply) occurring on an output before, during, and after output turn "on." When the CSB signal rises to the high logic state, the corresponding output is turned "on" and a delay timer activated. The duration of the delay timer is 25 to 100 s. If the short circuit takes place before the output is turned "on," the delay experienced is the entire 25 to 100 s followed by shutdown. If the short occurs during the delay time, the shutdown still occurs after the delay time has elapsed. If the short circuit occurs after the delay time, shut- down is immediate (within 20 s after sensing). The purpose of the delay timer is to prevent false faults from being reported when switching capacitive loads. If the SFPD pin is at 5.0 V (or VDD), an output will not be disabled when overcurrent is detected. The specific output will, within 5.0 to 10 s of encountering the short circuit, go into an analog current limited mode. This feature is especially useful when switching incandescent lamp loads, where high in-rush currents experienced during startup last for 10 to 20 ms. Each output of the MC33298 has its own overcurrent shutdown circuitry. Over temperature faults and the overvoltage faults are not affected by the SFPD pin. Both load current sensing and output voltage sensing are incorporated for Short Fault detection with actual detection occurring slightly after the onset of current limit. The current limit circuitry incorporates a SENSEFETTM approach to measure the total drain current. This calls for the current through a small number of cells in the power MOSFET to be measured and the result multiplied by a constant to give the total current. Whereas output shutdown circuitry measures the drain to source voltage and shuts down if a threshold (VThres) is exceeded. Short Fault detection is accomplished by sensing the output voltage and comparing it to VThres. The lowest VThres requires a voltage of 0.6 times 4.5 V (the minimum VDD voltage) or 2.7 V to be sensed. For an enabled output, with VDD = 5.0 0.5 V, an output voltage in excess of 4.4 V will be detected as a "short" while voltages less than 2.7 V will not be detected as "shorts." Over Current Recovery If the SFPD pin is in a high logic state, the circuit returns to normal operation automatically after the short circuit is removed (unless thermal shutdown has occurred). If the SFPD pin is grounded and overcurrent shutdown occurs; removal of the short circuit will result in the output remaining "off" until the next write cycle. If the short circuit is not removed, the output will turn "on" for the delay time (25 to 100 s) and then turn "off" for every write cycle commanding a turn "on." SFPD Pin Voltage Selection Since the voltage condition of the SFPD pin controls the activation of the short fault protection (i.e. shutdown) mode equally for all eight outputs, the load having the longest duration of in-rush current determines what voltage (state) the SFPD pin should be at. Usually if at least one load is, say an incandescent lamp, the in-rush current on that input will be milliseconds in duration. Therefore, setting SFPD at 5.0 V will prevent shutdown of the output due to the in-rush current. The system relies only on the Over Temperature Shutdown to protect the outputs and the loads. The MC33298 was designed to switch GE194 incandescent lamps with the SFPD pin in a grounded state. Considerably larger lamps can be switched with the SFPD pin held in a high logic state. Sometimes both a delay period greater than 25 to 100 s (current limiting of the output) followed by an immediate over current shutdown is necessary. This can be accomplished by programming the SFPD pin to 5.0 V for the extended delay period to afford the outputs to remain "on" in a current limited mode and then grounding it to accomplish the immediate shutdown after some period of time. Additional external circuitry is required to implement this type of function. An MCU parallel output port can be devoted to controlling the SFPD voltage during and after the delay period, is often a much better method. In either case, care should be taken to execute the SFPD start-up routine every time start-up or reset occurs. Undervoltage Shutdown An undervoltage VDD condition will result in the global shutdown of all outputs. The undervoltage threshold is between 2.5 V and 4.5 V. When VDD goes below the threshold, all outputs are turned "off" and the SO register is reset to indicate the same. An undervoltage condition at the VPWR pin will not cause output shutdown and reset. When VPWR is between 5.5 V and 9.0 V, the outputs will operate per the command word. However, the status as reported by the serial output (SO) pin may not be accurate. Proper operation at VPWR voltages below 5.5 V cannot be guaranteed. Deciphering Fault Type The MC33298 SO pin can be used to understand what kind of system fault has occurred. With eight outputs having open load, over current and over temperature faults, a total of 25 different faults are possible. The SO status word received by the MCU will be compared with the word sent to the MC33298 during the previous write cycle. If the two words are not the same, then the MCU should be programmed to determine which output or outputs are indicating faults. If the command bit for any of the output switches indicating a fault is high, the fault is an open load. The eight open load faults are therefore the ones most easily detected. Over current and over temperature faults are often related. Turning the affected output switches "off" and waiting for some time should make these faults go away. Over current and over temperature faults can not be differentiated in normal application usage. One advantage of the synchronous serial output is that multiple faults can be detected with only one pin (SO) being used for fault status indication. If VPWR experiences an overvoltage condition, all outputs will immediately be turned "off" and remain latched "off." A new command word is required to turn the outputs back "on" following an overvoltage condition.
MOTOROLA ANALOG IC DEVICE DATA
15
MC33298
Output Voltage Clamping Each output of the MC33298 incorporates an internal voltage clamp to provide fast turn-off and transient protection of the output. Each clamp independently limits the drain to source voltage to 65 V at drain currents of 0.5 A and keeps the output transistors from avalanching by causing the transient energy to be dissipated in the linear mode (see Figure 19). The total energy (EJ) can be calculated by multiplying the current area under the current curve (IA) during the time the clamp is active and the clamp voltage (VCL). Characterization of the output clamps, using a single pulse repetitive method at 0.5 A, indicate the maximum energy to be 100 mJ at 25C and 25 mJ at 125C per output. Using a single pulse non-repetitive method at 0.5 A the clamps are capable of 2.0 Joules at 25C and 0.5 Joules at 125C. Figure 19. Output Voltage Clamping
Drain-to-Source Clamp Voltage (VCL = 65 V) Drain Current (ID = 0.5 A) Clamp Energy (EJ = IA x VCL x t)
Drain Voltage
Drain-to-Source "On" Voltage (VDS(ON)) Gnd
VPWR Current Area (IA) Time
THERMAL CHARACTERIZATION
Thermal Model Logic functions take up a very small area of the die and generate negligible power. In contrast, the output transistors take up most of the die area and are the primary contributors of power generation. The thermal model shown in Figure 20 was developed for the MC33298 mounted on a typical PC board. The model is accurate for both steady state and transient thermal conditions. The components Rd0, Rd1, Rd2, ..., and Rd7 represent the steady state thermal resistance of the silicon die for transistor outputs 0, 1, 2, ..., and 7, while Cd0, Cd1, Cd2, ..., and Cd7 represent the corresponding thermal capacitance of the silicon die transistor outputs and plastic. The device area and die thickness determine the values of these specific components. The thermal impedance of the package from the internal mounting flag to the outside environment is represented by the terms Rpkg and Cpkg. The steady state thermal resistance of leads and the PC board make up the steady state package thermal resistance, Rpkg. The thermal capacitance of the package is made up of the combined capacitance of the flag and the PC board. The mold compound was not modeled as a specific component but is factored into the other overall component values. The battery voltage in the thermal model represents the ambient temperature the device and PC board are subjected to. The IPWR current source represents the total power dissipation and is calculated by adding up the power dissipation of each individual output transistor. This is easily done by knowing R DS(on) and load current of the individual outputs. Very satisfactory steady state and transient results have been experienced with this thermal model. Tests indicate the model accuracy to have less than 10% error. Output interaction with an adjacent output is thought to be the main contributor to the thermal inaccuracy. Tests indicate little or no detectable thermal affects caused by distant output transistors which are isolated by one or more other outputs. Tests were conducted with the device mounted on a typical PC board placed horizontally in a 33 cubic inch still air enclosure. The PC board was made of FR4 material measuring 2.5 by 2.5, having double-sided circuit traces of 1.0 oz. copper soldered to each device pin. The board temperature was measured with thermal couple soldered to the board surface one inch away from the center of the 16 device. The ambient temperature of the enclosure was measured with a second thermal couple located over the center and one inch distant from device. Thermal Performance Figure 20 shows the worst case thermal component parameters values for the MC33298 in the 20 pin plastic power DIP and the SOP-24 wide body surface mount package. The power DIP package has Pins 5, 6, 15, and 16 connected directly to the lead frame flag. The parameter values indicated take into account adjacent output cell thermal pulling effects as well as different output combinations. The characterization was conducted over power dissipation levels of 0.7 to 17 W. The junction-to-ambient temperature thermal resistance was found to be 37C/W with a single output active (31C/W with all outputs dissipating equal power) and in conjunction with this, the thermal resistance from junction to PC board (Rjunction-board) was found to be 27C/W (board temperature, measured 1 from device center). In addition, the thermal resistance from junction-to-heatsink lead was found to approximate 10C/W. Devoting additional PC board metal around the heatsinking pins improved Rpkg from 30 to 28C/W. The SOP-24 package has Pins 5, 6, 7, 8, 17, 18, 19, and 20 of the package connected directly to the lead frame flag. Characterization was conducted in the same manner as for the DIP package. The junction-to-ambient temperature resistance was found to be 40C/W with a single output active (34C/W with all outputs dissipating equal power) and the thermal resistance from junction-to-PC board (R junction-board) to be 30C/W (board temperature, measured 1 from device center). The junction-to-heatsink lead resistance was found again to approximate 10C/W. Devoting additional PC board metal around the heatsinking pins for this package improved the Rpkg from 33 to 31C/W. The total power dissipation available is dependent on the number of outputs enabled at any one time. At 25C the RDS(on) is 450 m with a coefficient of 6500 ppm/C. For the junction temperature to remain below 150C, the maximum available power dissipation must decrease as the ambient temperature increases. Figures 21 and 22 depict the per output limit of current at ambient temperatures necessary for the plastic DIP and SOP packages respectively when one, four, or eight outputs are enabled "on." Figure 23 depicts how the RDS(on) output value is affected by junction temperature. MOTOROLA ANALOG IC DEVICE DATA
MC33298
Figure 20. Thermal Model (Electrical Equivalent)
Junction Temperature Node VD = TD (C) (Volts represent Die Surface Temperature) Output 0 Output 1 Output 2 Output 6 Output 7
Rd0
Cd0
Rd1
Cd1
Rd2
Cd2
Rd6
Cd6
Rd7
Cd7
IPWR (Steady State or Transient) (1.0 A = 1.0 W of Device Power Dissipation)
Flag Temperature Node
Rpkg = Rleads + RPC Board
Cpkg = Cflag + CPC Board
Ambient Temperature Node VA = TA (C) (1.0 V = 1C Ambient Temperature) Package 20 Pin DIP SOP-24L Rdx ()* 7.0 7.0 Cdx (F)* 0.002 0.002 Rpkg ()* 30 33 Cpkg (F)* 0.2 0.15
* = C/W, F = W s/C, IPWR = W, and VA = C
MOTOROLA ANALOG IC DEVICE DATA
17
MC33298
Figure 21. Maximum DIP Package Steady State Output Current versus Ambient Temperature
3.0 1 Output "On" (37C/W) 2.5 2.0 1.5 4 Outputs "On" (32C/W) 1.0 0.5 8 Outputs "On" (31C/W) RDS(on) @ 150C = 0.8 TJ = 150C
I L(max), MAXIMUM CURRENT PER OUTPUT (A) ,
I L(max), MAXIMUM CURRENT PER OUTPUT (A) ,
Figure 22. Maximum SOP Package Steady State Ouput Current versus Ambient Temperature
2.5 1 Output "On" (40C/W) RDS(on) @ 150C = 0.8 TJ = 150C
2.0 1.5 1.0 0.5 0 - 50 8 Outputs "On" (34C/W) 4 Outputs "On" (35C/W)
0 - 50
- 25
0
25
50
75
100
125
150
- 25
0
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 23. Maximum Output "On" Resistance versus Junction Temperature
RDS(on) , OUTPUT "ON" RESISTANCE ( ) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 - 50 - 25 0 25 50 75 100 125 150 VPWR = 13 V VDD = 5.0 V IOUT = 0.5 A
TJ, JUNCTION TEMPERATURE (C)
18
MOTOROLA ANALOG IC DEVICE DATA
MC33298
Latch-Up Immunity Device latch-up caused by substrate injection has been characterized. Latch-up immunity has both a dc and a transient immunity component. DC latch-up immunity results indicate the device to be capable of withstanding in excess of four amps of reverse current out of any of the output transistors while the control logic continues to function normally. The logic control current (IDD) was found to increase by only 0.6 mA with four amps of current being pulled out of an output. Additionally, the IPWR current was found to increase by only 0.15 mA under the same condition. These increases are a result of minority carriers being injected into substrate and subsequently being collected. The following procedure has been developed to test for transient latch-up immunity and has been applied to this automotive circuit design. Results of transient testing indicate the device to operate properly at output currents greater than 1.5 A. The procedure tests for the device's immunity to intermittent load to battery current connection with the device controlling an inductive load. Appropriately termed "the file test," the battery is connected to a shop file while the lead to the inductive load is dragged across the files surface causing intermittent load opens producing lots of arcs, sparks, and smoke, plus severe transients (see Figure 24). It is during these severe transients that latch-up most likely could occur. The battery voltage used for this test was 18 V and the inductive load was 2.0 mH. These values were found to produce severe transient stresses of the device outputs. All outputs must maintain operation and input control during transient generation to pass "the file test." The device's input control currents were found to remain stable and were not affected by dc or transient latch-up immunity testing. Figure 24. Transient Latch-Up Immunity File Test
Battery
VPWR VDD SFPD Reset CSB
0.1 F Output 0 65 V Gate Control
Outputs 1-7
Open Load Detect Short Circuit Detect Over Temperature Detect
Ilimit RS
SCLK SI SO
Grounds
APPLICATIONS INFORMATION
SIOP Communication Two common communication protocols used in Motorola's microprocessors are the Serial Peripheral Interface (SPI) and Synchronous Input Output Port (SIOP). SIOP is a subset of the more flexible SPI and the simpler of the two protocols. SIOP is used on many of the MC68HC05 family of microcontrollers. Restrictions of the SIOP protocol include: 1) the SCLK frequency is fixed at one-fourth the internal clock rate and 2) the polarity of the SCLK signal is fixed. By way of example, the MC68HC05P9 utilizes SIOP protocol and is not directly compatible with the serial input requirements of the MC33298. Specifically, the MC33298 accepts data on the falling edge of SCLK whereas its rising edge triggers data transfer in the SIOP protocol. SCLK is high during SIOP transmissions, which is the opposite of what the MC33298 requires. Though designed specifically for SPI communication protocol, the MC33298 can easily be adapted to communicate with SIOP protocol through the use of software. The amount of code required to implement SPI in software is relatively small, so the only major drawback is a slower transfer of data. The software routine shown in Table 1 completes a transfer in about 100 s. Cost The bottom line relates to cost. The MC33298 is a very cost effective octal output serial switch for applications typically encountered in the automotive and industrial market segments. To accomplish only the most basic serial switch function the MC33298 offers, using a discrete semiconductor approach, would require the use of at least eight logic level power MOSFETs for the outputs and two shift registers for the I/O plus other miscellaneous "glue" components. Additional circuitry would have to be incorporated to accomplish the protection features offered by the MC33298. Other noteworthy advantages the MC33298 offers are conservation of power and board space, requirement of fewer application components, and enhanced application reliability. The MC33298 is available at a fraction of the cost required for discrete component implementation and represents true value. The MC33298 represents a cost effective device having advanced performance and features and worthy of consideration.
MOTOROLA ANALOG IC DEVICE DATA
19
MC33298
Table 1. Program to Exercise the MC33298 Using SPI (Having Only SIOP) Protocol
SET LABELS FOR OUTPUT REGISTERS PORTA PORTB PORTC PORTD DDRA DDRB DDRC DDRD DTOUT DATAIN VALUE DATA1 SCR SSR SDR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU ORG INIT RSP $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0080 $0081 $0082 $0083 $000A $000B $000C $0100 ;SPI Port ;DO (Data Out), SCLK, CS, RESET, X, FLTOUT, DI (Data In) ;Normally the SIOP Port. SIOP will be disabled ;A-D Converter Port ;Timer Capture Port ;Data Direction Register for SPI Port ;Data Direction Register for SCLK, SDI, SDO, 11111 ;Data Direction Register for A-D Converter Port ;Data Direction Register for PORTD, Timer Capture ;Register for the SPI output data. This register will be used for a Serial-to-Parallel transformation. ;Input Register for SPI. Also used for a Serial-to-Parallel transformation. ;Register to store the SPI. Also used for a Serial-to-Parallel transformation. ;Miscellaneous data register ;Label for SIOP control register, 0 SPE 0 MSTR 0 0 0 0. ;Label for SIOP status register, SPIF DCOL 0 0 0 0 0 0, Read Only Register. ;Label for SIOP data register. ;Program starts at first byte of User ROM. ;Reset Stack Pointer to $FF.
INITIALIZE THE DATA REGISTERS AND THEIR DATA DIRECTION BIT REGISTERS LDA STA #$FE DDRA ;Configuration PortA as the SPI Port. ;All but Bit 0 will be outputs.
LDA STA STA STA
#$FF DDRB DDRC DDRD ;Configure Register B as an output. SIOP is not used for the MC33298, but is available for another peripheral. ;Configure Register C as an output ;Configure Register D as an output
LDA STA
#%00010000 SCR
;Initialize the SIOP Control Register. ;Disable SIOP by clearing Bit 6.
SELECT THE DESIRED OUTPUTS TOP LDA STA BSET BCLR BSET #$55 VALUE 4,PORTA 4,PORTA 4,PORTA Select outputs of MC33298 to be turned "on." This instruction is left inside the loop to include changes while running the program. A set bit will cause the associated MC33298 output to be "off." The value register is uncorrupted by the serial-to-parallel conversion. ;Reset the MC33298. ;Also establishes a + or - trigger source ;The MC33298 is reset with a logic low.
BCLR
5,PORTA
;Enable MC33298 by pulling CSB (chip select bar) low. Within the MC33298 the Fault Status is transferred to the MC33298 Serial Register at a falling edge of CSB.
LDA STA
VALUE DTOUT
;Select outputs to be turned "on." ;Save Output Word (Value) to check for fault.
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MOTOROLA ANALOG IC DEVICE DATA
MC33298
SPI TRANSFER LOOP LDX #$07 ;Set the number of Read/Shift cycles.
LOOP
ASL ASL BCS BCLR JMP
DATAIN DTOUT DOONE 7,PORTA GOON 7,PORTA 6,PORTA
;Shift a Zero into LSB of DATAIN and ASL other bits. ;Test value currently in MSB of DTOUT. ; ;MSB was Zero, so clear DATA OUT bit.
DOONE GOON
BSET BSET
;MSB was One, so set the DATA OUT bit. ;Set the SCLK. Serial Output pin of the MC33298 changes state on the rising edge of the SCLK. Read the next bit coming from the MC33298.
BRCLR BSET
0,PORTA, WZZER0 0,DATAIN
;Read the bit and branch if Zero. LSB of DATAIN is already cleared due to the ASL above. ;Bit was One. Set the next bit in DATAIN.
WZZER0
BCLR DECX BPL
6,PORTA
;Clear SCLK. Falling edge causes the MC33298 to read the next bit from the MCU.
LOOP
;Continue to loop eight times until the SPI transfer is complete.
BSET
5,PORTA
;Transfer control signal to output transistors.
ESTABLISH A BRIEF DELAY LDA PAUSE DECA BNE BCLR JSR PAUSE 5,PORTA FLTCHK #16 ;3 Clock cycles ;3 Clock cycles ;Transfer output status to Serial Register. ;Jump to Fault Check subroutine.
JSR
DLY
;Delay 1/T msec
BSET BRA
5,PORTA TOP
;Deselect the MC33298. ;Return to top of loop.
SUBROUTINE TO CHECK FOR FAULTS FLTCHK BCLR LDA CMP BEQ BSET NOFLT RTS 1,PORTA DATAIN VALUE NOFLT 1,PORTA ;Check for Faults. ;If there is no Fault, continue. ;Activate Fault LED. ;CLR the Fault pin.
MOTOROLA ANALOG IC DEVICE DATA
21
MC33298
DELAY SUBROUTINE DLY STA LDA OUTLP INNRLP CLRX DECX BNE DECA BNE LDA RTS ORG FDB $1FF INIT OUTLP DATA1 INNRLP DATA1 #$04 ;Save Accumulator in RAM. ;Do outer loop 4 times, roughly 4.0 ms. ;X used as Inner Loop Count ;0-FF, FF-FE, ... 1-0 256 loops. ;6CYC* 256* 1.0 s/CYC = 1.53 ms ;4-3. 3-2, 2-1, 1-0 ;1545CYC* 4*1.0 s/CYC = 6.18 ms ;Recover Accumulator value. ;Return from subroutine.
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MOTOROLA ANALOG IC DEVICE DATA
MC33298
OUTLINE DIMENSIONS
P SUFFIX PLASTIC PACKAGE CASE 738-03 DIP (16+2+2) ISSUE E -A -
20 11
B
1 10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0 15 1.01 0.51
-T - SEATING PLANE E G F D 20 PL 0.25 (0.010) N
K M
J 20 PL 0.25 (0.010)
M
M
T
B
M
TA
M
DW SUFFIX PLASTIC PACKAGE CASE 751E-04 SOP (16+4+4)L ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
MOTOROLA ANALOG IC DEVICE DATA
23
MC33298
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
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MOTOROLA ANALOG IC DEVICE DATA
*MC33298/D*
MC33298/D

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